diff options
| author | Vito G. Graffagnino <vito@graffagnino.xyz> | 2022-08-30 16:06:22 +0100 |
|---|---|---|
| committer | Vito G. Graffagnino <vito@graffagnino.xyz> | 2022-08-30 16:06:22 +0100 |
| commit | f1eabbaa1b4ff1836d0ee8335b31d009203f3775 (patch) | |
| tree | bbe77eacaef8ab8a5999e517c3006973c9e3e44c /snippets/vhdl.snippets | |
| parent | 823302458ec6c53455a3f34674415c43ce6a3187 (diff) | |
fixed zathura integration with texlab using nvim-texlabconfig
Diffstat (limited to 'snippets/vhdl.snippets')
| -rw-r--r-- | snippets/vhdl.snippets | 137 |
1 files changed, 0 insertions, 137 deletions
diff --git a/snippets/vhdl.snippets b/snippets/vhdl.snippets deleted file mode 100644 index 0683a21..0000000 --- a/snippets/vhdl.snippets +++ /dev/null @@ -1,137 +0,0 @@ -# -## Libraries - -snippet lib - library ${1} - use $1.${2} - -# Standard Libraries -snippet libs - library IEEE; - use IEEE.std_logic_1164.ALL; - use IEEE.numeric_std.ALL; - -# Xilinx Library -snippet libx - library UNISIM; - use UNISIM.VCOMPONENTS.ALL; - -## Entity Declaration -snippet ent - entity ${1:`vim_snippets#Filename()`} is - generic ( - ${2} - ); - port ( - ${3} - ); - end entity $1; - -## Architecture -snippet arc - architecture ${1:behav} of ${2:`vim_snippets#Filename()`} is - - ${3} - - begin - - - end $1; - -## Declarations -# std_logic -snippet st - signal ${1} : std_logic; -# std_logic_vector -snippet sv - signal ${1} : std_logic_vector (${2} downto 0); -# std_logic in -snippet ist - ${1} : in std_logic; -# std_logic_vector in -snippet isv - ${1} : in std_logic_vector (${2} downto 0); -# std_logic out -snippet ost - ${1} : out std_logic; -# std_logic_vector out -snippet osv - ${1} : out std_logic_vector (${2} downto 0); -# unsigned -snippet un - signal ${1} : unsigned (${2} downto 0); -## Process Statements -# process -snippet pr - process (${1}) - begin - ${2} - end process; -# process with clock -snippet prc - process (${1:clk}) - begin - if rising_edge ($1) then - ${2} - end if; - end process; -# process with clock and reset -snippet prcr - process (${1:clk}, ${2:nrst}) - begin - if ($2 = '${3:0}') then - ${4} - elsif rising_edge($1) then - ${5} - end if; - end process; -# process all -snippet pra - process (${1:all}) - begin - ${2} - end process; -## Control Statements -# if -snippet if - if ${1} then - ${2} - end if; -# if -snippet ife - if ${1} then - ${2} - else - ${3} - end if; -# else -snippet el - else - ${1} -# if -snippet eif - elsif ${1} then - ${2} -# case -snippet ca - case ${1} is - ${2} - end case; -# when -snippet wh - when ${1} => - ${2} -# for -snippet for - for ${1:i} in ${2} ${3:to} ${4} loop - ${5} - end loop; -# while -snippet wh - while ${1} loop - ${2} - end loop; -## Misc -# others -snippet oth - (others => '${1:0}'); |
